Solutions for implementing voice and/or image recognition tasks in an integrated circuit encounter challenges of losing data precision or accuracy due to limited resources in the integrated circuit. For example, a single low-power chip (e.g., ASIC or FPGA) for voice or image recognition tasks in a mobile device is typically limited in chip size and circuit complexity by design constraints. A voice or image recognition task implemented in such low-power chip cannot use data that has the same numeric precision, nor can it achieve the same accuracy when performing the same task in a processing device of a desktop computer. For example, an artificial intelligence (AI) integrated circuit (i.e., an AI chip) in a mobile phone may have an embedded cellular neural network (CeNN) architecture that has only 5 bits per channel to represent data values, whereas a processor in a desktop computer or a server in a cloud computing environment uses a 32-bit floating point or 64-bit double-precision floating point format. In another example, the CeNN architecture of an AI chip may have a low resolution at 224×224 as opposed to a higher resolution (e.g., 1 Megabytes(M), 2M, or even 12M, 20M) available in modern imaging capturing devices. As a result, image or voice recognition models, such as a convolutional neural network, when trained on desktop or server computers and transferred to an integrated circuit with low resolution, low bit-width or low numeric precision, will suffer a loss in performance.
This patent disclosure is directed to systems and methods for addressing the above issues and/or other issues.